1. Field of the Invention
The invention pertains to the field of computing technology and microelectronics and is useful in producing high- speed integrated circuits and sets of integrated circuits for digital signal processing, for computing product sums, for multiplication and addition processes.
2. Description of the Related Art
The device for computing product sums is known, containing eight 2-bit input data bus, sixteen input buffer elements, four 2 -bit conveyer adders of the first layer, 4 blocks of results normalization of the first layer, two conveyor adders of the second layer, two blocks of results normalization of the second layer, output conveyor adder of the third layer, two intermediate flip-flops, output normalization block, two output buffer flip-flops, two output buffer elements, input of the main clocking signals, "end of word" input signal, control signal input, control block including shifter, two one-bit result outputs, each adder includes two output flip-flops, a carry flip-flop and combinational two-bit adder consisting of two combination 1-bit complete adders, input of the main clocking signal, "end of word" signal input, two one-bit outputs, each of normalization blocks of the first and second layer includes delay flip-flop, controlling "end of word" input, commutator, two one-bit inputs and two one-bit outputs, normalization block of the third layer includes one-bit charge inputs: "end of word" input, control signal input, two delay flip-flops, two commutators, And - No gate, control block shifter includes seven flip-flops, elements connections are organized in the order of their listing ([1], p. 107-125).
The described device realizes the principle (for case m=0): ##EQU1##
Here
C--computing product sums results. PA1 A.sub.i --i of operand; PA1 2.sup.m --weighting of operand PA1 a.sub.ij -j--bit of Ai operand PA1 2.sup.m+j- weighting of a.sub.ij bit PA1 n--capacity of operands A.sub.i PA1 C--result of computing product sums; PA1 a.sub.i -i--bit of A operand; PA1 b.sub.j -j--bit of B operand; PA1 a.sub.i *b.sub.j --partial products; PA1 2.sup.i+j- partial product weighting; PA1 n--capacity of operands. PA1 high-speed specialized, sectional processors with parallel and parallel-pipelining data processing but these devices have limited functional capabilities and large hardware expenses; PA1 one-crystal programmable processors but they have unsufficient speed for data processing in real time scale [3]. PA1 C--computing product sums results; PA1 A--multiplicand; PA1 B--multiplier; PA1 b.sub.i - i--multiplier capacity; PA1 A*b.sub.i --partial product; PA1 2.sup.i --partial product weighting; PA1 n--a multiplier capacity. PA1 increase of speed (reduction of delay); PA1 increase of throughput; PA1 reduction of hardware expenses; PA1 architectural flexibility and circuit simplification (circuit uniformity and regularizing); PA1 expansion of functional capabilities. PA1 computing of k.sub.p m.sub.p -capacity summands 2*k.sub.p clock cycles will be required, herewith the clock cycle time corresponds to time of switching of typical logic element; PA1 computing partial product sum of one pair of m.sub.p -bit numbers will require 2*m.sub.p clock cycles herewith the clock-cycle time corresponds to time of switching of the typical logic elements; PA1 computing of one pair of m.sub.p -bit numbers will require 2*m.sub.p +2 clock cycle herewith the clock cycle time corresponds to time of switching of typical logic element. PA1 strengthening of computing efficiency (considerable reduction of operations number of multiplication and addition, occupied memory capacity); PA1 absolute accuracy of signals reproduction without noise which can be described by of polynome. ##EQU4## PA1 t--time; PA1 a.sub.k --polynomial coefficient; PA1 n--number of polynome members PA1 simplicity of signal description adgustment to polynomial form; PA1 improvement of the characteristic of signal-to-noiseratio at the filtration with less discretization frequency; PA1 X.sub.i --i of multiplicand; PA1 Y.sub.i --i of multiplier; PA1 n--number of product sum. PA1 K.sub.0 =f(0) PA1 K.sub.1 =f(1)-f(0) PA1 K.sub.2 =1/2f(0)-f(2/4)+1/2f(1) PA1 K.sub.3 =-3/8f(0)+f(1/4)-3/4f(2/4)+1/8f(1) PA1 A.sub.3 =21.[3]K.sub.3 PA1 A.sub.2 =-32K.sub.3 +4K.sub.2 PA1 A.sub.1 =10.[6]K.sub.3 -4K.sub.2 +K.sub.1 PA1 A.sub.0 =K.sub.0 PA1 A.sub.3 =-8f(0)+21.[3]f(1/4)-16f(2/4)+2.[6]f(1) PA1 A.sub.2 =14f(0)-32f(1/4)+20f(2/4)-2f(1) PA1 A.sub.1 =-7f(0)+10.[6]f(1/4)-4f(2/4)+0.[3]f(1) PA1 A.sub.0 =f(0)
However, the described device can't computing product sums of A.sub.i .times.2.sup.i- type or sums of partial products of a.sub.1.sup.x b.sub.j.sup.x 2.sup.i+j type and so can't be applied in multipliers.
The device for computing product sums is known, working in two modes: computation of partial product sums of two pairs of 8-bit numbers, computation of one pair of 16-bit numbers. The device is two-channel with processing of two bits in clock cycle in each channel.
The device includes four blocks of adders, six conversion circuits of the direct code into compliment, two full 2-bit adders with carry storage, two normalization blocks, sign digit circuit, control block, four output buffer flip-flops, clocking signal input, "end of word" character accompanying signal input, initial set signal input, working mode selection input, two 2-bit output data bus, each adder block includes seven 2-bit conveyor adders with carry storage, each device adder includes 5 flip-flops, two full 1-bit combinational adders, four one-bit inputs, two one-bit outputs, each circuit of the converter of the direct code into complement includes four flip-flops, two commutators, analysis circuit, four 1-bit inputs, two 1-bit outputs, the sign digit circuit includes six flip-flops, one EXCLUSIVE OR gate, four 1-bit data inputs, signal input of "end of word" character accompaning, five 1-bit outputs, each normalization block includes three flip-flops, one commutator, control strobe of character dump, two 1-bit inputs, two one-bit outputs, all elements are connected in the following sequence: four blocks of adder, four code converters, two adders, two normalization blocks, two code convertors, four input buffer flip-flops ([1], p. 54-84).
The device computes partial product sums of a.sub.i *b.sub.j type i.e. realizes the principle: ##EQU2##
Here
However the device doesn't form partial a.sub.i *b.sub.j products and so can't be complete functional block for multiplication.
The device for computing product sums is known, working in two modes; computing of 16-bit numbers products; computing of two product sums of 8-bit numbers. The device includes the above mentioned device as well as eight input buffer flip-flops, four 8-bit (two including four) working registers of reception and storage of input operands, two impulse allocators, two circuits of partial product formation, two commutators of partial product, three other commutator, input of storage mode selection; each circuit of partial product formation includes four AND gates blocks and four delay flip-flops, each block includes four AND gates ([1], p. 54-84). Devices described above are industrial patterns of BIC K1815B.PHI.1 and K1815IIM1 of the speed microprocessor BIC set of K1815 series for digital signal processing.
Description of these devices in the directory is completely based on the inventions descriptions to author's certificates the authors of most of them are the directory's authors [2]. Complete comparative analysis of methods, procedures, adders, multipliers, for speed BIC sets building for digital signals processing is given in the directory, and considered parallel pipelining principles of computing organization are applied in the best world analogous up to the present time.
However is can be seen from principles of devices function that maximum speed and productivity can be achieved if n-capacities are processed in each clock cycle under condition that operands capacity is n, but herewith the hardware expenses increases sharply, particular those which are necessary for adders trees building. Data processing in parallel-sequential code creates technical complexity for records of summands weightings, creates the necessity of circuits availability for parallel code conversion into parallel-sequential code as ADC give the number in the parallel code.
The best world analogous of devices, capable to carry out functions of computing product sums can be divided into two classes: